• DocumentCode
    2879000
  • Title

    A 45ns 16 × 16 CMOS multiplier

  • Author

    Kaji, Yuichi ; Sugiyama, N. ; Kitamura, Yoshifumi ; Ohya, S. ; Kikuchi, Masashi

  • Author_Institution
    NEC Corp., Kanagawa, Japan
  • Volume
    XXVII
  • fYear
    1984
  • fDate
    22-24 Feb. 1984
  • Firstpage
    84
  • Lastpage
    85
  • Abstract
    A 16 × 16 parallel multiplier, using 1.5μm design rule N-well CMOS technology, will be covered. A multiply time of 45ns has been achieved by using Booth´s algorithm and Wallace tree reduction. The typical power dissipation is 100mW.
  • Keywords
    Adders; CMOS technology; Circuit synthesis; Digital signal processing chips; Energy consumption; FETs; Large scale integration; MOS devices; Registers; Space technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1984.1156616
  • Filename
    1156616
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2879000