Title :
Mapping algorithms for a multi-bit data path processing reconfigurable chip RHW
Author :
Yamauchi, Tsukasa ; Nakaya, Shogo ; Inuo, Takeshi ; Kajihara, Nobuki
Abstract :
While FPGAs are mainly used for implementing general purpose logic circuits, the RHW works with the CPU to accelerate the computation intensive part of the application by reconfiguring its data paths and ALUs optimized for the algorithm. Hence the RRW was designed to implement multi-bit data paths and ALUs efficiently. We developed a new architecture that consists of a two-dimensional array of multi-bit original ALU that is composed of a type of adder with multi-functional pre-logics
Keywords :
adders; field programmable gate arrays; reconfigurable architectures; CPU; FPGA; RHW; adder; computation intensive; data path reconfiguration; general purpose logic circuits; mapping algorithms; multi-bit data path processing; multi-functional pre-logic; reconfigurable architecture; reconfigurable chip; two-dimensional array; Adders; Application software; Field programmable gate arrays; Laboratories; Logic circuits; Logic devices; Logic functions; National electric code; Reconfigurable logic; Routing;
Conference_Titel :
Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-7695-0871-5
DOI :
10.1109/FPGA.2000.903921
