• DocumentCode
    2879083
  • Title

    A 16ns 2K × 8b CMOS SRAM

  • Author

    Okazaki, Naonobu ; Komatsu, Teruhisa ; Hoshi, Nobukazu ; Tsuboi, Kazuo ; Shimada, Toshikazu

  • Author_Institution
    Sony Semicond. Group, Kanagawa, Japan
  • Volume
    XXVII
  • fYear
    1984
  • fDate
    22-24 Feb. 1984
  • Firstpage
    88
  • Lastpage
    89
  • Abstract
    This report will cover a 2K × 8b SRAM using 1.5μm CMOS technology with platinum silicide gate electrodes and single layer aluminum. Typical access time is 16ns, and power dissipation is 150mW at 1MHz.
  • Keywords
    Aluminum; CMOS process; Delay effects; Delay lines; MOS devices; Power measurement; Random access memory; Read-write memory; Switches; Time measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1984.1156620
  • Filename
    1156620
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2879083