Challenges in Temperature Cycling Test for Electronic Packages Containing Low-K/Cu Silicon

The cavity-down thermally enhanced tape ball grid array (TBGA) package has generally challenged the assembly industry on passing package qualification requirement especially temperature cycling requirement when assembling low-k/Cu wafers. A mechanical stress simulation was conducted in order to assess the stress distribution in the low-k region of the silicon in the TBGA configuration. The simulation analysis indicated that the existing TBGA package applies a tensile stress on the top portion of die edge region where the inter-layer dielectric (ILD) stacks are located when the package is subjected to temperature cycling tests. A series of experiments was designed to validate the prediction of the mechanical simulation model. The knowledge of the stress distribution in the TBGA system enabled us to obtain an optimal solution for the combination of low-k dies and TBGA package to pass industrial-level qualification.