DocumentCode
2879503
Title
A VLSI communication processor designed for testability
Author
Sacarisen, S. ; Stambaugh, M. ; Lou, P. ; Khosrovi, A. ; Ki Chang
Author_Institution
Texas Instruments, Inc., Houston, TX, USA
Volume
XXVII
fYear
1984
fDate
22-24 Feb. 1984
Firstpage
172
Lastpage
173
Abstract
A 16b processor for control of digital communication networks, with 2186 bytes of RAM will be discussed. The chip features include instruction fault detection, I/O parity check/ generation and special test modes.
Keywords
Circuit faults; Circuit noise; Circuit testing; Decoding; Hardware; Logic testing; Process design; Read only memory; Registers; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1984.1156646
Filename
1156646
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