Title :
A GaAs 4Kb SRAM with direct coupled FET logic
Author :
Hirayama, Motoko ; Ino, M. ; Matsuoka, Yasutaka ; Suzuki, M.
Author_Institution :
NTT Atsugi Electrical Comm. Lab., Kanagawa, Japan
Abstract :
A GaAs 4Kb × 1 SRAM with DCFL using self-aligned implantation for N+- layer technology will be discussed. The SRAM has been measured at a 5ns address access time with 700mW dissipation.
Keywords :
Circuit simulation; FETs; Gallium arsenide; Logic; MESFETs; Monitoring; Power dissipation; Random access memory; Read-write memory; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156647
