• DocumentCode
    2879527
  • Title

    A GaAs 4Kb SRAM with direct coupled FET logic

  • Author

    Hirayama, Motoko ; Ino, M. ; Matsuoka, Yasutaka ; Suzuki, M.

  • Author_Institution
    NTT Atsugi Electrical Comm. Lab., Kanagawa, Japan
  • Volume
    XXVII
  • fYear
    1984
  • fDate
    22-24 Feb. 1984
  • Firstpage
    46
  • Lastpage
    47
  • Abstract
    A GaAs 4Kb × 1 SRAM with DCFL using self-aligned implantation for N+- layer technology will be discussed. The SRAM has been measured at a 5ns address access time with 700mW dissipation.
  • Keywords
    Circuit simulation; FETs; Gallium arsenide; Logic; MESFETs; Monitoring; Power dissipation; Random access memory; Read-write memory; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1984.1156647
  • Filename
    1156647
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2879527