Title :
A CMOS floating point multiplier
Author :
Uya, M. ; Kaneko, Kunihiko ; Yasui, J.
Author_Institution :
Matsushita Central Res. Lab., Osaka, Japan
Abstract :
A dual port 512×10b RAM using single poly NMOS technology will be described. The memory provides separate access ports and internally resolves access request conflicts to simplify data linking between asynchronous processors. The worst case access time is 200ns. Power dissipation is 350mW at 3.7MHz.
Keywords :
CMOS technology; Clocks; Digital signal processing chips; Laboratories; Multiplexing; Power dissipation; Propagation delay; Registers; Semiconductor device measurement; Time measurement;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156653
