Title :
Merged current mode logic
Author :
Zdebel, P. ; Engl, W.
Author_Institution :
Institut fur Theoretische Elektrotechnik, Aachen, Germany
Abstract :
The use of down and up transistors to form nonsaturating and merged current mode logic resulting in a power-delay product of 0.1pJ for power dissipation less than 50μW/gate and a minimum delay of 1.6ns at 200μW/gate will be described.
Keywords :
Bipolar transistors; Dielectrics; Geometry; Inverters; Isolation technology; Logic devices; MOSFET circuits; Merging; Testing; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156657
