DocumentCode
2879809
Title
A 55ns CMOS EEPROM
Author
Zeman, Robert ; Chun Ho ; Chang, Ting-Hao
Author_Institution
Excel Microelectronics, Inc., San Jose, CA
Volume
XXVII
fYear
1984
fDate
22-24 Feb. 1984
Firstpage
144
Lastpage
145
Abstract
A 32,768 (4K×8) CMOS EEPROM with a 55ns address access time will be discussed. Access time through the memory array was accomplished by using two memory cells per bit. A differential signal is generated on complementary bit lines to reduce the voltage swing necessary for sensing.
Keywords
Delay effects; Differential amplifiers; EPROM; Low voltage; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1984.1156661
Filename
1156661
Link To Document