Title :
A CMOS 12K gate array with flexible 10Kb memory
Author :
Takechi, Masaru ; Ikuzaki ; Itoh, Takayuki ; Fujita, Masayuki ; Asano, Masahiro ; Masaki, A. ; Matsunaga, Tsuneo
Author_Institution :
Hitachi Device Dev. Center, Tokyo, Japan
Abstract :
A 2μm CMOS gate with transistors throughout the wiring region, suitable for implementing both 12,000 logic gates and 10,000 bits of memory will be described. A single array with 16-word×8bits of RAM (access time of 16ns) and a 16-word×10b first in/first-out memory, will also be covered.
Keywords :
CMOS logic circuits; Delay estimation; Logic circuits; Logic design; Logic gates; Random access memory; Read-write memory; Strontium; Very large scale integration; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156670
