Silicon, Low-K Dielectric, and Nano-Scale Metal Interface Characterization Using Stress-Engineered Superlayer Test Methods

Thin film layers are utilized in emerging microelectronics, optoelectronics, and MEMS devices. Typically these thin film layers are composed of different materials with dissimilar properties. A common mode of failure for thin films is delamination caused by external loading or intrinsic stress present in the materials. To characterize bonded thin film material systems, it is necessary to measure the interfacial fracture toughness. When material thicknesses approach micro and nano scales, interfacial fracture toughness measurement is a challenging task. Accordingly, innovative test techniques need to be developed to study interfacial fracture parameters. The ongoing research at Georgia Institute of Technology is developing fixtureless delamination test techniques that can be used to measure interfacial properties of nano-and micro-scale thin films. The modified decohesion test (MDT) and the single-strip decohesion test (SSDT) are such fixtureless tests under development. In these tests a thin film interface material of interest is deposited on a substrate and delamination is driven by a superlayer material with high intrinsic stress sputter-deposited on-top of the interface material. A deposited release layer material allows for the contact area between the interface material and the substrate to be controlled. These tests differ in geometry but share the same generic methodology and can be used for a number of material systems over a wide range of mode mixity. This paper presents the methodology and implementation of the MDT and SSDT tests and compares results to better understand their scope. A case study of the interfacial fracture toughness as a function of mode mixity for titanium and silicon interface was performed to determine which test should be used for low-k dielectric (Black Diamond^TM) and tantalum. Lastly, ongoing research on low-k and tantalum interface is discussed.