DocumentCode
2880038
Title
Sampling rate and quantification density control in VHDL-AMS
Author
Hervé, Yannick ; Snaidero, Sébastien
Author_Institution
CNRS-ERM, Illkirch-Graffenstaden, France
fYear
2002
fDate
6-8 Oct. 2002
Firstpage
90
Lastpage
93
Abstract
VHDL-AMS allows designers to describe a system with time dependent equations. If they want to plot a curve y=f(x), it becomes hard to ensure the sampling rate and the quantification density of x and y values. This paper submits a very simple method to control it using a little utility model written in VHDL-AMS, called the "Q_fier".
Keywords
density control; hardware description languages; sampling methods; Q_fier; VHDL-AMS; quantification density control; sampling rate; time dependent equations; Analog computers; Application specific processors; Computational modeling; Convergence; Equations; Magnetic hysteresis; Sampling methods; Signal design; Testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Behavioral Modeling and Simulation, 2002. BMAS 2002. Proceedings of the 2002 IEEE International Workshop on
Print_ISBN
0-7803-7634-X
Type
conf
DOI
10.1109/BMAS.2002.1291064
Filename
1291064
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