Title :
A 20ns 64K CMOS SRAM
Author :
Minato, O. ; Masuhara, T. ; Sasaki, T. ; Sakai, Yoshiki ; Hayashida, T.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A 19.0mm264K×1 SRAM utilizing pulsed-word-line technique, P-well/bipolar technology, and 1.3μm gate MOS transistors, will be described. The RAM has typical address access time of 20ns and power dissipation of 70mW at 1 MHz cycle time.
Keywords :
CMOS technology; Clocks; Electrical resistance measurement; Frequency; MOS devices; MOSFETs; Power dissipation; Random access memory; Read-write memory; Semiconductor device measurement;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156700
