Title :
A 30ns 64K CMOS RAM
Author :
Hardee, K. ; Griffus, M. ; Galvas, R.
Author_Institution :
Inmos Corp., Colorado Springs, CO, USA
Abstract :
This paper will describe a 30ns 64K×1 CMOS SRAM using analog circuit techniques, multistage decoding, and a single polysilicon memory cell with a buried vss line.
Keywords :
Circuits; Clamps; Decoding; Differential amplifiers; Energy consumption; Fault tolerance; MOS devices; Random access memory; Read-write memory; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156702
