Author :
Ozawa, Toshihiro ; Koshimaru, S. ; Kudo, O. ; Itoh, Hayato ; Harashima, Noboru ; Yasuoka, Nami ; Asai, Hiroki ; Yamanaka, T. ; Kikuchi, Shinji
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
A 25ns 64K×1 CMOS SRAM with a 30.9mm2chip size will be covered in this paper. P-well 11.5μm CMOS technology features a double metal poly load 4-transistor memory cell.
Keywords :
Aluminum; CMOS technology; Clocks; Conductors; Equalizers; Integrated circuit interconnections; MOSFETs; Power dissipation; Random access memory; Read-write memory;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156703
