The CMOS analog multiplier free from mobility reduction

Author

Dejhan, Kobchai ; Suwanchatree, N. ; Chaisayun, Pipat Prommee Ittipong

Author_Institution

Fac. of Eng., King Mongkut´´s Inst. of Technol., Bangkok, Thailand

Volume

1

fYear

2004

fDate

26-29 Oct. 2004

Firstpage

23

Abstract

In this paper, a CMOS analog multiplier circuit is proposed. It consists of eight voltage subtractors, four voltage sources and a multiplier cell. Its major advantage is its freedom from mobility reduction, so it has low total harmonic distortion (THD). For the proposed multiplier cell, its inputs are applied to the drains of the input cell transistors through the voltage sources. Their gates are fixed to the same bias voltage to remove the effect of mobility reduction. The simulation results show that the THD is less than 0.13% for 0.8 V_P-P input signal at 2.5 V supply voltage, and that the -3 dB bandwidth is up to 38 MHz.

Keywords

CMOS analogue integrated circuits; analogue multipliers; carrier mobility; harmonic distortion; 0.8 V; 2.15 mW; 2.5 V; 38 MHz; CMOS analog multiplier; low THD; mobility reduction free multiplier; multiplier cell; total harmonic distortion; voltage sources; voltage subtractors; Asia; Bandwidth; CMOS analog integrated circuits; CMOS technology; Information technology; Linearity; MOSFETs; Signal generators; Threshold voltage; Total harmonic distortion;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technology, 2004. ISCIT 2004. IEEE International Symposium on

Print_ISBN

0-7803-8593-4

Type

conf

DOI

10.1109/ISCIT.2004.1412442

Filename

1412442