• DocumentCode
    2880657
  • Title

    A 28ns CMOS SRAM with bipolar sense amplifiers

  • Author

    Miyamoto, Jun ; Saitoh, Shohei ; Momose, H. ; Shibata, Hajime ; Kanzaki, K. ; Iizuka, Tetsuya

  • Author_Institution
    Toshiba Semicond. Device Engin. Lab., Kawasaki, Japan
  • Volume
    XXVII
  • fYear
    1984
  • fDate
    22-24 Feb. 1984
  • Firstpage
    224
  • Lastpage
    225
  • Abstract
    This report will discuss a 64K×1 SRAM with bipolar sense amplifiers, utilizing both CMOS and bipolar devices with double poly 1.2μm MoSi processing. The SRAM typically accesses in 28ns and has a 20nA standby mode.
  • Keywords
    CMOS process; CMOS technology; Circuits; Delay lines; Packaging; Propagation delay; Random access memory; Regulators; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1984.1156709
  • Filename
    1156709
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2880657