DocumentCode
2880668
Title
A design of four-quadrant analog multiplier
Author
Dejhan, Kobchai ; Prommee, Pipat ; Tiamvorratat, Wanlop ; Mitatha, Somsak ; Chaisayun, Ittipong
Author_Institution
Fac. of Eng., King Mongkut´´s Inst. of Technol., Bangkok, Thailand
Volume
1
fYear
2004
fDate
26-29 Oct. 2004
Firstpage
29
Abstract
The paper proposes a new four-quadrant analog multiplier which consists of a multiplier cell, a mixed signal circuit and three signal subtraction circuits. Its advantages are: the design has single ended inputs; the geometry of all the transistors is equal; its output can be the product of two signal voltage, or the product of a signal current and a signal voltage. Simulation results are demonstrated by PSpice to confirm the operation of the circuit.
Keywords
MOSFET circuits; analogue multipliers; linear network synthesis; voltage multipliers; PSpice; four-quadrant analog multiplier; mixed signal circuit; multiplier cell; signal subtraction circuits; Asia; Circuit simulation; Filters; Frequency modulation; Geometry; Information technology; MOSFETs; Power supplies; Signal design; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications and Information Technology, 2004. ISCIT 2004. IEEE International Symposium on
Print_ISBN
0-7803-8593-4
Type
conf
DOI
10.1109/ISCIT.2004.1412443
Filename
1412443
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