Electrical-Optical High Speed Serial Server Scalability Link

Increased demand for performance has driven a significant increase in the data rate and the complexity of today´s high speed systems and interconnect. While skin effects and dielectric loss are significant sources of limitation of current high-speed digital communication (Broomall and Van Deusen, 1997), equalization at the transmitter, receiver, and interconnect has extended the range and performance of copper links. Electrical copper links are typically used to interconnect multiple processor subsystems to build symmetric multi-processor (SMP) systems, as well as to connect input/output (I/O) subsystems across relative long distances. During the electrical design and validation of a highly scalable, modular SMP server (Brown and Dhawan, 2002) with data rates of 3.2 GT/s (GigaTransfers per second) and higher, a test vehicle was designed and built. The goal was to characterize and contrast an all-copper external cable and a copper-to-optical interconnect technology, and to understand how to achieve the overall system design goals from the perspective of link performance, electrical challenges, and physical design constraints. Key design parameters have been modeled and correlated with laboratory measurements such as AC coupling capacitor selection and layout optimization, via stub, back-drilling, and signal launch effects. Modeling techniques and correlation challenges are discussed in this paper.