Title :
Performance limits of NMOS and CMOS
Author :
Pfiester, J. ; Shott, J. ; Meindl, J.
Author_Institution :
Stanford University, Stanford, CA
Abstract :
An analytic MOST model to project circuit performance limits will be reported. Minimum channel lengths of 0.14 and 0.40μm, corresponding to logic gate delays of 19ps for CMOS and 103ps for NMOS are predicted.
Keywords :
CMOS technology; Circuits; Dynamic voltage scaling; Electron devices; MOS devices; Paper technology; Semiconductor device modeling; Switches; Threshold voltage; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156715
