Compact Physical Models for Power Supply Noise and Chip/Package Co-Design of Gigascale Integration

Compact physical models are derived for predicting power supply noise of chips in the gigascale integration (GSI) era. These models consider both IR-drop and simultaneous switching noise (SSN) and give a quick full waveform description of the first droop power supply noise as well as its peak value. The derivation of these models proceeds by considering a frequency domain representation of power grids and later obtaining time domain equivalents. The derived models enable chip/package co-design in current and future technology nodes by allowing a designer to make tradeoffs in various chip and package parameters such as on-chip wire area, number and sizes of power/ground I/O pads and amount of decoupling capacitance. SPICE simulations show that the worst case peak noise model has less than 4% error.