Top-down structured parallelisation of embedded image and vision applications

The authors propose an architecture-independent structured top-down design methodology for parallel embedded systems. This methodology proceeds from the observation that embedded signal processing systems may be characterized as consisting of series of independent processing stages. The methodology proposes mapping this sequential software structure to a generalized parallel architecture for embedded systems based upon a pipeline of stages with well-defined data communication patterns between them. Each stage of the pipeline then exploits parallelism in the most appropriate way, for example data parallelism applied at various different levels, algorithmic parallelism, or temporal multiplexing of complete input data sets. Processor farming, which is easily adapted to all of these models of parallelism, has been proposed as a general implementation method, because it allows indefinite incremental scaling of any stage and results in a single tractable analytical model