DocumentCode
2880942
Title
A 280ps Josephson 4b × 4b parallel multiplier
Author
Jun´ichi Sone ; Jaw-Shen Tsai ; Ema, S. ; Abe, H.
Author_Institution
NEC Microelectronics Research Labs., Kawasaki, Japan
Volume
XXVIII
fYear
1985
fDate
13-15 Feb. 1985
Firstpage
220
Lastpage
221
Abstract
A 4b×4b multiplier with 350ps multiplication time and 1mW dissipation that has been built with 249 resistor-coupled Josephson logic gates will be described. Circuits were fabricated in a Pb-alloy process with 5μ minimum line widths and junction diameters.
Keywords
Arithmetic; Circuit testing; Delay effects; Delay estimation; Delay lines; Electrodes; Power dissipation; Propagation delay; Semiconductor device measurement; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1985.1156724
Filename
1156724
Link To Document