High Performance Coreless Flip-Chip BGA Packaging Technology

This paper described the shadow moire measurement of bare flip chip coreless and standard (3/2/3) BGA substrate to inspect the change of each thermal history (0 hr, after pre-baking, IR-refiow), the warpage increased significantly on IR reflow peak temperature and largest warpage located around the C4 area of coreless FCBGA substrate and standard FCBGA substrate change was not obvious. Electrical performance was simulated by Ansoft Q3D and HFSS software, the coreless flip chip BGA substrate showed higher insertion loss and lower return loss than standard (3/2/3) flip chip BGA substrate. Bump stress, die stress and Cu trace stress of substrate were simulated by FEA (Finite Element Analysis) method, the results indicate that coreless flip chip BGA performs lower die stress and bump stress and higher trace stress than standard (3/2/3) flip-chip BGA. Furthermore, this study also found out the optimal assembly process condition. For the reliability evaluation, all of packages were subjected to pre-condition of JEDEC Level 3, TCT (temperature cycling test), HTSL (high temperature storage life) and HAST (high accelerated stress test) and the results showed passed.