DocumentCode :
2881208
Title :
A 256K dual port memory
Author :
Ishimoto, S. ; Nagami, A. ; Watanabe, Hiromi ; Kiyono, J. ; Hirakawa, Naoto ; Okuyami, Y. ; Hosokawa, F. ; Tokushige, K.
Author_Institution :
NEC Corp., Kawasaki, Japan
Volume :
XXVIII
fYear :
1985
fDate :
13-15 Feb. 1985
Firstpage :
38
Lastpage :
39
Abstract :
This paper will describe a 64K×4 DRAM and a 256×4 serial readout memory with an access time of 35ns developed to provide graphic data pickup from any location. The ×4 DRAM port affords independent write capability for each bit in the word.
Keywords :
Blanking; Character generation; Circuits; Content addressable storage; DH-HEMTs; Displays; Random access memory; Read-write memory; Registers; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
Type :
conf
DOI :
10.1109/ISSCC.1985.1156740
Filename :
1156740
Link To Document :
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