An area-efficient VLSI architecture for Reed-Solomon decoder

Author

Guo, Yan-Fei ; Li, Zhan-Cai ; Wang, Qin

Author_Institution

Adv. Comput. & Commun. Res. Center, University of Sci. & Technol., Beijing, China

Volume

2

fYear

2005

fDate

12-14 Oct. 2005

Firstpage

1194

Lastpage

1198

Abstract

In this paper, the known decoding procedure for Reed-Solomon (RS) code is analyzed in the way of vector operations that are suitable for VLSI implementation and pipelining. Then, a new area-efficient architecture for RS decoder is proposed. The new architecture can improve the reuse rate of main computation unit, reduce the hardware complexity and delete the redundancy circuit. The results show that the total number of gates of the proposed RS (204,188) decoder is about 27,000 gates, which is about 39% smaller than the same kind of conventional ones. It has been integrated in a channel demodulation chip for high-definition television (HDTV) and the chip has been tested successfully in practice.

Keywords

Reed-Solomon codes; VLSI; high definition television; pipeline processing; HDTV; RS decoder; Reed-Solomon decoder; area-efficient VLSI architecture; channel demodulation chip; hardware complexity reduction; high-definition television; pipelining; redundancy circuit deletion; Circuits; Computer architecture; Decoding; Demodulation; HDTV; Hardware; Pipeline processing; Reed-Solomon codes; TV; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technology, 2005. ISCIT 2005. IEEE International Symposium on

Print_ISBN

0-7803-9538-7

Type

conf

DOI

10.1109/ISCIT.2005.1567083

Filename

1567083