Title :
A 8K × 8 SRAM with an internal power down design
Author :
Sood, L. ; Golab, J. ; Leiss, J. ; Yee-Chaung See ; Barnes, John
Author_Institution :
Motorola, Inc., Austin, TX, USA
Abstract :
A 35ns CMOS SRAM with 55mA active (50ns cycle time) power drain will be reported. Internal chip selection is broken down in several blocks to reduce power surges. A 1.5μ twin-well CMOS technology with polycide gate was employed.
Keywords :
Artificial intelligence; Random access memory; Timing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156782
