• DocumentCode
    2881901
  • Title

    A 8K × 8 SRAM with an internal power down design

  • Author

    Sood, L. ; Golab, J. ; Leiss, J. ; Yee-Chaung See ; Barnes, John

  • Author_Institution
    Motorola, Inc., Austin, TX, USA
  • Volume
    XXVIII
  • fYear
    1985
  • fDate
    13-15 Feb. 1985
  • Firstpage
    66
  • Lastpage
    67
  • Abstract
    A 35ns CMOS SRAM with 55mA active (50ns cycle time) power drain will be reported. Internal chip selection is broken down in several blocks to reduce power surges. A 1.5μ twin-well CMOS technology with polycide gate was employed.
  • Keywords
    Artificial intelligence; Random access memory; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1985.1156782
  • Filename
    1156782
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2881901