DocumentCode
2882571
Title
SuperV back-end design flow based on Astro
Author
Donghui, Wang ; Qian, Yu ; Ying, Hong ; Chaohuan, Hou
Author_Institution
Inst. of Acoust., Chinese Acad. of Sci., Beijing, China
Volume
2
fYear
2005
fDate
12-14 Oct. 2005
Firstpage
1524
Lastpage
1527
Abstract
In deep sub-micron VLSI design, designers must face many challenges including timing, area, power, IR drop, crosstalk, etc. A back-end design flow is put forward based on Astro. The flow has been used in SuperV DSP microprocessor back-end design for timing optimization, area and IR drop reduction, crosstalk prevention, etc. The final chip includes more than 1 million gates. The area is 5 mm × 5 mm. The clock frequency is up to 266 MHz, and power dissipation no more than 1 watt.
Keywords
VLSI; crosstalk; digital signal processing chips; integrated circuit design; Astro; DSP microprocessor; SuperV back-end design flow; clock frequency; deep sub-micron VLSI; gates; power dissipation; CMOS technology; Clocks; Crosstalk; Design optimization; Digital signal processing chips; Frequency; Manufacturing; Microprocessors; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications and Information Technology, 2005. ISCIT 2005. IEEE International Symposium on
Print_ISBN
0-7803-9538-7
Type
conf
DOI
10.1109/ISCIT.2005.1567162
Filename
1567162
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