DocumentCode
2882683
Title
New Strategies for System Level Design
Author
Gajski, Daniel D.
Author_Institution
Center for Embedded Comput. Syst., California Univ., Irvine, CA
fYear
2006
fDate
26-28 April 2006
Firstpage
1
Lastpage
5
Abstract
With complexities of systems-on-chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. The obvious solution that comes to mind is increasing levels of abstraction, or in other words, increasing the size of the basic building blocks. However, it is not clear what these basic blocks should be and what should be the strategy for creating a SOC out of these basic blocks. To make things more difficult, the difference between software and hardware is becoming indistinguishable which, in turn, requires sizable change in the industrial and academic infrastructure
Keywords
integrated circuit design; logic design; system-on-chip; circuit complexities; logic synthesis; system level design; systems-on-chip; Algorithm design and analysis; Design methodology; Hardware; History; Integrated circuit modeling; Logic; Productivity; Software design; Software prototyping; System-level design;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location
Hsinchu
Print_ISBN
1-4244-0179-8
Electronic_ISBN
1-4244-0180-1
Type
conf
DOI
10.1109/VDAT.2006.258106
Filename
4027478
Link To Document