• DocumentCode
    2882746
  • Title

    Differential split-level CMOS logic for sub-nanoseconds speeds

  • Author

    Pfennings, L. ; Mol, W. ; Bastiaens, J. ; van Dijk, Jan

  • Author_Institution
    Philips Research Labs., Eindhoven, Netherlands
  • Volume
    XXVIII
  • fYear
    1985
  • fDate
    13-15 Feb. 1985
  • Firstpage
    212
  • Lastpage
    213
  • Abstract
    This paper will discuss subnanosecond gate delays (0.8ns) obtained for complex logic gates designed with cascode-coupled NMOS-PMOS loads, differential logic NMOS trees, and interconnect lines with 2.4V swings.
  • Keywords
    Adders; CMOS logic circuits; DSL; Degradation; Delay; Implants; Integrated circuit interconnections; Testing; Threshold voltage; Transconductance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1985.1156827
  • Filename
    1156827
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2882746