DocumentCode
2882848
Title
A 3.6ns ECL programmable array logic IC
Author
Millhollan, M. ; Chiakang Sung
Author_Institution
National Semiconductor Corp., Santa Clara, CA, USA
Volume
XXVIII
fYear
1985
fDate
13-15 Feb. 1985
Firstpage
202
Lastpage
203
Abstract
An ECL FPAL with a total delay of 3.6ns at 1.0W will be reported. The chip has 64 product terms with 16 inputs and 8 outputs.
Keywords
Capacitance; Cutoff frequency; Electronics packaging; Fuses; Logic arrays; Logic circuits; Logic programming; Programmable logic arrays; Propagation delay; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1985.1156833
Filename
1156833
Link To Document