• DocumentCode
    2882865
  • Title

    A CMOS Variable Gain Amplifier with DC Offset Calibration Loop for Wireless Communications

  • Author

    Cheng, Zhih-Siou ; Bor, Jenn-Chyou

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., HsinChu
  • fYear
    2006
  • fDate
    26-28 April 2006
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A 64 dB gain range VGA with DC offset calibration loop is proposed in this work. This VGA adopts the degeneration type amplifier to vary voltage gain and uses the super-source-follower input stage to enhance the linearity. A digital-based DC offset calibration loop is also designed to solve the DC offset problem. An experimental chip is fabricated in 0.18 mum process. With 2 dB step, the gain error is less than 0.8 dB and the output DC offset is less than 100mV at maximum gain setting. The total power consumption is 11 mW
  • Keywords
    CMOS integrated circuits; amplifiers; radiocommunication; 0.18 micron; 11 mW; 64 dB; CMOS variable gain amplifier; DC offset calibration loop; wireless communications; Attenuation; Calibration; Circuits; Digital control; Dynamic range; Gain; Linearity; Noise figure; Voltage; Wireless communication;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation and Test, 2006 International Symposium on
  • Conference_Location
    Hsinchu
  • Print_ISBN
    1-4244-0179-8
  • Electronic_ISBN
    1-4244-0180-1
  • Type

    conf

  • DOI
    10.1109/VDAT.2006.258115
  • Filename
    4027487
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2882865