Title :
A 90ns 1Mb DRAM with multi-bit test mode
Author :
Kumanoya, M. ; Fujishima, Kenzaburo ; Tsukamoto, Kazuya ; Nishimura, Yasutaro ; Saito, Kazuyuki ; Matsukawa, T. ; Yoshihara, Tatsuhiko ; Nakano, T.
Author_Institution :
Mitsubishi Electric Corp., Itami, Japan
Abstract :
A 1Mb DRAM using a half Vcc biased memory cell with a reduced electric field of 2MV/cm will be reported. A shared sense amplifier design and a continous nibble mode are also included. Additionally, a test pin allows testing as a 256K×4 memory. Die is 65mm2.
Keywords :
Capacitors; Circuit testing; Clocks; MOS devices; Random access memory; Read-write memory; Redundancy; Switches; Tellurium; Variable structure systems;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156837
