Design Trade-offs for Low-power and High Figure-of-merit LNA

Author

Chen, Hsien-Ku ; Sha, J.R. ; Chang, Da-Chiang ; Juang, Ying-Zong ; Chiu, Chin-Fong

Author_Institution

Nat. Appl. Res. Labs., National Chip Implementation Center, Hsinchu

fYear

2006

fDate

26-28 April 2006

Firstpage

1

Lastpage

4

Abstract

We report a 5.4 mW ultra low dc power low noise amplifier (LNA) at 5.5 GHz, which is based on a 0.35-mum BiCMOS technology. The trade-off between the NF and linearity for LNA circuit design has been investigated. Furthermore, the usage of the HBT-cascade-MOS methodology is simultaneously satisfied the tradeoff between noise figure (NF) and linearity of LNA. This amplifier achieves a gain/(NF times P_DC) ratio figure of merit of 0.774 (1/mW) which is the better reported at 5~6-GHz band and suitable for wireless LAN applications

Keywords

BiCMOS integrated circuits; MOS integrated circuits; bipolar integrated circuits; integrated circuit design; low noise amplifiers; low-power electronics; 0.35 micron; 5.4 mW; 5.5 GHz; BiCMOS technology; HBT-cascade-MOS methodology; LNA linearity; low noise amplifier; noise figure; wireless LAN; BiCMOS integrated circuits; Circuit noise; Circuit topology; Heterojunction bipolar transistors; High power amplifiers; Integrated circuit noise; Linearity; Noise figure; Noise measurement; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2006 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

1-4244-0179-8

Electronic_ISBN

1-4244-0180-1

Type

conf

DOI

10.1109/VDAT.2006.258117

Filename

4027489