DocumentCode
2883120
Title
Design of a shared memory Carrier Ethernet switch compliant to Provider Backbone Bridging-Traffic Engineering (IEEE802.1Qay)
Author
Mehta, Saurabh ; Upadhyaya, Ashutosh ; Bidkar, Sarvesh ; Gumaste, Ashwin
Author_Institution
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Mumbai, India
fYear
2012
fDate
24-27 June 2012
Firstpage
29
Lastpage
35
Abstract
Carrier Ethernet is emerging as a new transport paradigm across metropolitan and core networks. Provider Backbone Bridging-Traffic Engineering or PBB-TE was standardized in the IEEE as 802.1Qay as a mechanism to provide a dedicated transport service at the Ethernet layer. This paper discusses implementation of the PBB-TE standard using shared memory switch architecture, though the same architecture argument can be extended to implement MPLS-TP (the other manifestation of Carrier Ethernet). While shared memory switch architectures have been well investigated, we provide to the best of our knowledge the first carrier-class aggregation switch implemented in a single Field Programmable Gate Array (FPGA). This low-cost implementation paves the way for advances in Carrier Ethernet technologies to be made available to the access part of the network using rapid prototyping and commercial off the shelf components. The switch architecture supports multiple QoS levels and implements circuit emulation to transport traditional circuit services over a packet backbone. A rigorous simulation study validates our effort.
Keywords
field programmable gate arrays; local area networks; metropolitan area networks; quality of service; telecommunication switching; telecommunication traffic; Ethernet layer; IEEE802.1Qay; QoS level; carrier Ethernet technology; carrier-class aggregation switch; circuit emulation; commercial off the shelf component; core network; dedicated transport service; field programmable gate array; metropolitan network; packet backbone; provider backbone bridging-traffic engineering; rapid prototyping; shared memory carrier Ethernet switch design; shared memory switch architecture; transport paradigm; Fabrics; Memory architecture; Memory management; Quality of service; Standards; Switches; PBB-TE; switch architecture;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Switching and Routing (HPSR), 2012 IEEE 13th International Conference on
Conference_Location
Belgrade
ISSN
Pending
Print_ISBN
978-1-4577-0831-2
Electronic_ISBN
Pending
Type
conf
DOI
10.1109/HPSR.2012.6260824
Filename
6260824
Link To Document