Title :
A 240K transistor CMOS array with flexible allocation of memory and channels
Author :
Takahashi, Hiroki ; Sato, Seiki ; Goto, Gensuke ; Nakamura, T. ; Kikuchi, Hiroaki ; Shirato, Toru
Author_Institution :
Fujitsu Laboratories, Ltd., Atsugi, Japan
Abstract :
A CMOS masterslice will be reported, covering the design of basic cells to accommodate both logic unit and memory cells, wiring channels allocated in discrete units and logic and memory blocks placed in arbitrary positions of a cell array. Implementation of a 16×16b parallel multiplier with 16b×64w SRAM and 16b×256w ROM will be compared.
Keywords :
CMOS logic circuits; Laboratories; Large-scale systems; Latches; Logic arrays; Logic design; Logic gates; Random access memory; Read only memory; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156853
