Title :
An Efficient Field-Partition Based Code Compression and Its Pipelined Decompression System
Author :
Jeang, Yuan-Long ; Lin, Yong-Zong
Author_Institution :
Dept. of Electr. Eng., Nat. Kaohsiung Univ. of Appl. Sci.
Abstract :
A field partition based instruction compression/decompression system for ARM series architecture is proposed. Due to a high degree of repetition in the encoding of the specific fields of the instructions in a program, we could get a statistics of the appearances of each field in all instructions of a program. Depending on the statistics, we partition each instruction into three fields and compress each field using Huffman coding method. Experimental results show that our method is better than others with a 55% of average compression ratio. For decompression, single buffering, double buffering and pipeline techniques have been proposed. However, due to jump penalty, these techniques incur more delays in pipeline or have to stop and fill in the cache buffers. We proposed a pipeline with back-up for flushing technique that incurs no delay and without stopping due to jump. The average performance is increased about 10% to 60%
Keywords :
Huffman codes; cache storage; data compression; encoding; logic partitioning; microprocessor chips; ARM series architecture; Huffman coding method; cache buffers; code compression; double buffering; encoding; field partition; instruction compression system; instruction decompression system; pipeline techniques; pipelined decompression system; single buffering; Costs; Delay; Dictionaries; Electronic mail; Encoding; Energy consumption; Huffman coding; Pipelines; Reduced instruction set computing; Statistics;
Conference_Titel :
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0179-8
Electronic_ISBN :
1-4244-0180-1
DOI :
10.1109/VDAT.2006.258133