DocumentCode
2883208
Title
A 1Mb DRAM with a folded capacitor cell structure
Author
Horiguchi, F. ; Itoh, Yoshio ; Iizuka, Hideo ; Ogura, M. ; Masuoka, Fujio
Author_Institution
Toshiba VLSI Res. Center, Kawasaki, Japan
Volume
XXVIII
fYear
1985
fDate
13-15 Feb. 1985
Firstpage
244
Lastpage
245
Abstract
This report will describe a NMOS DRAM with a folded capacitor cell (
2) fabricated using buried oxide isolation and two level metalization. Typical
access time is 30ns. Active power dissipation ia 270mW at 260ns cycle time.
2) fabricated using buried oxide isolation and two level metalization. Typical
access time is 30ns. Active power dissipation ia 270mW at 260ns cycle time.Keywords
Aluminum; Capacitance; Capacitors; Circuits; FCC; Isolation technology; MOS devices; Milling machines; Random access memory; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1985.1156855
Filename
1156855
Link To Document