Title :
A 75MS/s Low Power Pipeline ADC with scalable Resolution
Author :
Muthers, David ; Tielert, Reinhard
Author_Institution :
Kaiserslautern Univ.
Abstract :
A low power pipeline ADC with selectable resolutions of 13bit and 11bit has been implemented. The maximum sampling rate is 75MS/s. In 13bit mode the power consumption is 49mW and the SINAD 67.4dB for a 0.5MHz signal. In 11 bit mode it consumes 26mW, the SINAD is 62.1dB for a 0.5MHz signal. The low power consumption has been achieved by omitting building blocks that are not absolutely essential for a pipeline ADC, like an active S&H or a common-mode regulation
Keywords :
analogue-digital conversion; low-power electronics; pipeline processing; sample and hold circuits; 0.5 MHz; 11 bit; 13 bit; 26 mW; 49 mW; active sample-and-hold circuit; common mode regulation; pipeline analog-to-digital converters; Bandwidth; Capacitors; Circuits; Clocks; Energy consumption; Pipelines; Sampling methods; Signal processing; Signal resolution; Topology;
Conference_Titel :
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0179-8
Electronic_ISBN :
1-4244-0180-1
DOI :
10.1109/VDAT.2006.258135
