Title :
A 4K CMOS gate array with automatically-generated test circuits
Author :
Kuboki, S. ; Masuda, I. ; Hayashi, Teruaki ; Torii, Shuichi
Author_Institution :
Hitachi Research Laboratory, Ibaraki, Japan
Abstract :
A testable 4K CMOS array using a scan bus and a 2μ process on a 7.2×7.0mm2chip will be described. The cell structure and D/A system supports 98-100% dc fault testing without logic design restrictions in a chip area of 5%.
Keywords :
Automatic testing; Circuit faults; Circuit testing; Clocks; Latches; Logic design; Logic testing; Master-slave; Test pattern generators; Timing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156857
