DocumentCode
2883239
Title
A 16-levels/cell dynamic memory
Author
Aoki, Masaki ; Nakagome, Y. ; Horiguchi, M. ; Ikenaga, S. ; Shimohigashi, K.
Author_Institution
Hitachi Ltd., Tokyo, Japan
Volume
XXVIII
fYear
1985
fDate
13-15 Feb. 1985
Firstpage
246
Lastpage
247
Abstract
A 4b(16-level)/cell storage, single transistor dynamic memory circuit having a four × density storage advantage over conventional DRAMs will be discussed. R/W operation was observed with storage level of 80-100mV.
Keywords
Capacitance; Circuit testing; Costs; Large scale integration; Operational amplifiers; Preamplifiers; Pulse amplifiers; Read-write memory; Threshold voltage; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1985.1156858
Filename
1156858
Link To Document