Title :
A 16-levels/cell dynamic memory
Author :
Aoki, Masaki ; Nakagome, Y. ; Horiguchi, M. ; Ikenaga, S. ; Shimohigashi, K.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A 4b(16-level)/cell storage, single transistor dynamic memory circuit having a four × density storage advantage over conventional DRAMs will be discussed. R/W operation was observed with storage level of 80-100mV.
Keywords :
Capacitance; Circuit testing; Costs; Large scale integration; Operational amplifiers; Preamplifiers; Pulse amplifiers; Read-write memory; Threshold voltage; Timing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156858
