Title :
Thermal-Driven Interconnect Optimization by Simultaneous Gate and Wire Sizing
Author :
Lin, Yi-Wei ; Chang, Yao-Wen
Author_Institution :
Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
Abstract :
Temperature, as well as electromigration (EM), area, timing, and power, has become one of the most important concerns in nanometer circuit design. In this paper, we model the effects of thermal on both interconnect delay and EM reliability. Applying the least square estimator (LSE) method, we develop a posynomial formula to approximate interconnect temperature and present an algorithm to optimally solve the simultaneous interconnect temperature, EM, area, delay, and power optimization by sizing circuit components based on Lagrangian relaxation. Experimental results show that our algorithm is very effective, efficient, and economical
Keywords :
circuit optimisation; electromigration; integrated circuit interconnections; least squares approximations; relaxation theory; Lagrangian relaxation; electromigration; gate sizing; interconnect delay; interconnect temperature; least square estimator method; power optimization; thermal effects; thermal-driven interconnect optimization; wire sizing; Circuit synthesis; Delay effects; Delay estimation; Electromigration; Integrated circuit interconnections; Least squares approximation; Optimization methods; Temperature; Timing; Wire;
Conference_Titel :
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0179-8
Electronic_ISBN :
1-4244-0180-1
DOI :
10.1109/VDAT.2006.258147
