DocumentCode
2883602
Title
Adaptive Quadrature Clock Generator
Author
Huang, Juin-Hau ; Lin, Chih Hsien ; Jou, Shyh-Jye
Author_Institution
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li
fYear
2006
fDate
26-28 April 2006
Firstpage
1
Lastpage
4
Abstract
In this paper we propose the architecture for multi-phases clocking distribution. Based on QCG architecture, we propose a new adaptive QCG to increase its operation frequency range. The adaptive QCG can automatically track and lock phase difference when input frequency is different. This architecture is implemented by UMC 0.13mum 1P8M process and employed by on-chip transceiver. The average power consumption is 6.43 mW at 2 GHz clocking frequency. The operation frequency is from 500 MHz to 2.5 GHz
Keywords
clocks; integrated circuit design; 0.13 micron; 0.5 to 2.5 GHz; 6.43 mW; QCG architecture; adaptive quadrature clock generator; multiphase clocking distribution; on-chip transceiver; operation frequency range; phase difference; Bandwidth; Clocks; Delay lines; Energy consumption; Frequency; Microprocessors; Phase locked loops; Routing; Timing; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location
Hsinchu
Print_ISBN
1-4244-0179-8
Electronic_ISBN
1-4244-0180-1
Type
conf
DOI
10.1109/VDAT.2006.258160
Filename
4027532
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