• DocumentCode
    2883629
  • Title

    A 30ns 256K full CMOS SRAM

  • Author

    Okazaki, Naonobu ; Miyaji, F. ; Kobayashi, Kaoru ; Harada, Y. ; Aoyama, J. ; Shimada, Toshikazu

  • Author_Institution
    Sony Semiconductor Group, Kanagawa, Japan
  • Volume
    XXIX
  • fYear
    1986
  • fDate
    19-21 Feb. 1986
  • Firstpage
    204
  • Lastpage
    205
  • Abstract
    This paper will cover a 32K×8 full CMOS SRAM with a divided word line that has been fabricated in single-poly, double-metal, P-well CMOS, Address access time is 30ns. Standby power dissipation is 500mW. The CMO5 memory cell using 6 transistors, designed in 1.0μm layout rules, measures 10.6μm \\times 13.2\\mu m.
  • Keywords
    Artificial intelligence; CMOS technology; Driver circuits; Isolation technology; MOSFETs; Paper technology; Power dissipation; Random access memory; Read-write memory; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
  • Conference_Location
    Anaheim, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1986.1156880
  • Filename
    1156880
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2883629