Title :
A Multi-Code Compression Technique for Reducing System-On-Chip Test Time
Author :
Shieh, Hong-Ming ; Wu, Chun-Shien ; Li, Jin-Fu
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Jungli
Abstract :
With the nano-scale technology, a system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes the complexity of SOC testing is much higher than testing conventional VLSI chips. One of the test challenges of SOCs is test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time. A multi-code decompressor for recovering the compressed test data is also proposed. Experimental results show that the MCC scheme can achieve higher compression ratio than the single-code compression schemes. The area cost of the multi-code decompressor is small - only about 3498mum2 based on TSMC 0.18mum standard cell technology
Keywords :
VLSI; integrated circuit design; integrated circuit testing; system-on-chip; 0.18 micron; VLSI chips; multicode compression; nanoscale technology; reusable cores; system-on-chip design; system-on-chip test time; Automatic test equipment; Automatic testing; Channel capacity; Cost function; Laboratories; Power system reliability; System testing; System-on-a-chip; Test data compression; Very large scale integration;
Conference_Titel :
VLSI Design, Automation and Test, 2006 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0179-8
Electronic_ISBN :
1-4244-0180-1
DOI :
10.1109/VDAT.2006.258169
