Title :
CMOS erasable programmable logic with zero standby power
Author :
Sau Wong ; Hock So ; Chuan Hung ; Jung Ou
Author_Institution :
Altera Corporation, Santa Clara, CA, USA
Abstract :
Programmable logic ICs with a complexity of up to 2000 gates will be reported. An input transition detector powers up the circuits and differential logic in the critical speed paths affords a 25ns delay.
Keywords :
CMOS logic circuits; CMOS memory circuits; Chip scale packaging; Delay; EPROM; Feedback; Latches; Programmable logic arrays; Programmable logic devices; Switches;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1986 IEEE International
Conference_Location :
Anaheim, CA, USA
DOI :
10.1109/ISSCC.1986.1156900
