DocumentCode :
2884137
Title :
Deconstructing commit
Author :
Bell, Gordon B. ; Lipasti, Mikko H.
Author_Institution :
Dept. of Elec. & Comp. Engr., Wisconsin-Madison Univ., Madison, WI, USA
fYear :
2004
fDate :
2004
Firstpage :
68
Lastpage :
77
Abstract :
Many modern processors execute instructions out of their original program order to exploit instruction-level parallelism and achieve higher performance. However even though instructions can execute in an arbitrary order, they must eventually commit, or retire from execution, in program order. This constraint provides a safety mechanism to ensure that mis-speculated instructions are not inadvertently committed, but can consume valuable processor resources and severely limit the degree of parallelism exposed in a program. We assert that such a constraint is overly conservative, and propose conditions under which it can be relaxed. This paper deconstructs the notion of commit in an out-of-order processor, and examines the set of necessary conditions under which instructions can be permitted to retire out of program order. It provides a detailed analysis of the frequency and relative importance of these conditions, and discusses microarchitectural modifications that relax the in-order commit requirement. Overall, we found that for a given set of processor resources our technique achieves speedups of up to 68% and 8% for floating point and integer benchmarks, respectively. Conversely, because out-of-order commit allows more efficient utilization of cycle-time limiting resources, it can alternatively enable simpler designs with potentially higher clock frequencies.
Keywords :
instruction sets; processor scheduling; program compilers; clock frequencies; commit deconstruction; cycle-time limiting resources; floating point; in-order commit; instruction-level parallelism; integer benchmarks; microarchitectural modifications; out-of-order commit; out-of-order processor; processor resources; processor scheduling; program order; resource utilization; safety mechanism; Clocks; Computer aided instruction; Dynamic scheduling; Microarchitecture; Out of order; Parallel processing; Processor scheduling; Protection; Resource management; Safety;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Performance Analysis of Systems and Software, 2004 IEEE International Symposium on - ISPASS
Print_ISBN :
0-7803-8385-0
Type :
conf
DOI :
10.1109/ISPASS.2004.1291357
Filename :
1291357
Link To Document :
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