An interleaved delta-sigma analog to digital converter with digital correction

Although delta-sigma modulators are widely used for low to moderate rate analog-to-digital conversion, the time over-sampling requirement has limited their application to higher rate converters. This paper presents an architecture wherein multiple delta-sigma modulators are combined with time interlacing. Instead, the system achieves the effect of over-sampling from the multiplicity of delta-sigma modulators. For a system containing M Lth order delta-sigma modulators, approximately L bits of accuracy are gained for every doubling of M. A major benefit of the architecture is that it retains much of robustness of the individual delta-sigma modulators to non-ideal circuit behavior. As a result, the architecture offers the potential of integrating high-precision, high-speed ADC together with digital signal processing functions using VLSI processes optimized for digital circuitry. Because of parallelism, the performance of the architecture is hugely degraded by channel mismatches. A digital technique is used to overcome this problem. The paper presents the general architecture and provides a performance analysis closely supported by computer simulations.