Computer-based design for tomorrow´s super chip

Through the 60s and early 70s, computer-design aids gathered relatively minor attention from the IC design community. By the early 80s, leading-edge design teams began taking on very complex designs, and it was rapidly discovered that traditional methods for design were breaking down. As a result, efforts were initiated to improve computer design aids, and for the first time, computer-aided-design (CAD) gained status as a necessary discipline for chip design. Today´s chip designers are facing a further explosion of IC complexity. Additionally, there is a need to reduce design time dramatically. Designers, together with CAD tool developers, are responding to these needs by experimenting with and developing a variety of new design methods that are in tune with computer automation. Clear trends are emerging from these efforts. A majority of the new design methods rely on the use of a high degree of regularity and structure, and most depend on initial optimization at a high architectural level followed by a partitioning of the chip into regular blocks. A design method that typifies the trends of today is structred custom. In this style, a chip is first partitioned into blocks such as PLA, ROM, RAM or data path, then the blocks are automatically generated using a block compiler, interconnect between blocks is performed manually, but has structure through abutment, buses and combs. Structured custom can produce die size and performance comparable to full custom, but with a much shorter design time. A second major design method which is gaining momentum is the macro-cell. In this approach, the chip is partitioned into large blocks as cited, but automatic routers that can deal with irregular block shapes can be used for interconnect. Dramatic improvements in design time are expected and performance and die size can approach full custom. Macro-cell and its variants will solve a large portion of the problems future designers face, but not all. Special situations will still - all for a full custom (or symbolic layout) approach, and large regular arrays will continue to find a niche for prototyping. The next evolutionary step is expected to be based on expert system-overlays used in conjunction with block compilers and macro-cell place and route tools. Such a system would help the experienced chip designer avoid known pit falls, and would guide tile less-skilled user through a complex design. This talk will address these developments and assess the role of the computer design environment that will support these new methods which would consist of a collection of baseline tools (e.g., simulators, custom layouts, verifications) and the advanced tools (e.g., block compilers, test, auto place and route) which would all be integrated into a single unifying data structure. The common data structure would permit rapid movement of large design bases between tools, and allow experimentation with new design methods. The tools will be technology independent to permit, for example, changing a complex design rule set with minimal effort. Most importantly, the system will provide a uniform interactive environment for creating rapidly a competitive ULSI chip from a high level description.