SALVO process for sub-50 nm low-V/sub T/ replacement gate CMOS with KrF lithography

Author

Chang, C.-P. ; Vuang, H.-H. ; Baker, M.R. ; Pai, C.S. ; Klemens, F.P. ; Miner, J.F. ; Mansfield, W.M. ; Kleiman, R.N. ; Kornbllit, A. ; Baumann, F.H. ; Rogers, S.N. ; Bude, M. ; Grazul, J.L. ; Lloyd, E.J. ; Frei, M. ; Sorsch, T.W. ; Cirelli, R. ; Ferry, E

Author_Institution

Lucent Technol. Bell Labs., Murray Hill, NJ, USA

fYear

2000

fDate

10-13 Dec. 2000

Firstpage

53

Lastpage

56

Abstract

We present the SALVO CMOS process, first device data and simulation study with the following features: (1) self-aligned local channel implants for SCE reduction; (2) sub-50 nm fabrication using only current production tools; (3) replacement gate with dual-polysilicon for low V/sub T/; (4) low aspect-ratio gates with CD insensitive to lithography and etch profile variability. The first demonstration of SALVO process shows it is a viable candidate for future ULSI CMOS production, in view of its versatility, controllability and compatibility.

Keywords

CMOS integrated circuits; ULSI; etching; ion implantation; photolithography; 25 to 50 nm; SALVO process; ULSI; compatibility; controllability; dual-polysilicon; etch profile variability; low aspect-ratio gates; low-V/sub T/ replacement gate CMOS; photolithography; self-aligned local channel implants; CMOS process; Controllability; Etching; Fabrication; Implants; Lithography; Production; Silicides; Tin; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2000. IEDM '00. Technical Digest. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-6438-4

Type

conf

DOI

10.1109/IEDM.2000.904257

Filename

904257